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| davicom semiconductor, inc. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus data sheet preliminary version: DM9302-ds-p01 july 30, 2009
DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 2 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 content 1. general description............................................................................................... 9 2. block diagram........................................................................................................... 9 3. features .................................................................................................................... 10 4. pin configuration : 64 pin lqfp.......................................................................... 11 5. pin description ........................................................................................................ 12 5.1 processor bus interface .................................................................................................... ........................... 12 5.2 eeprom interfaces .......................................................................................................... ............................. 12 5.3 led pins ................................................................................................................... ...................................... 13 5.4 clock interface............................................................................................................ ................................... 13 5.5 network interface .......................................................................................................... ................................ 13 5.6 miscellaneous pins ......................................................................................................... .............................. 14 5.7 power pins ................................................................................................................. .................................... 14 5.8 strap pins table........................................................................................................... ................................... 14 6. control and status register set................................................................... 15 6.1 network control register (00h) ............................................................................................. ...................... 17 6.2 network status register (01h).............................................................................................. ....................... 17 6.3 tx control register (02h).................................................................................................. ........................... 18 6.4 rx control register (05h) .................................................................................................. .......................... 18 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 3 DM9302-15-ds-p01 july 30, 2009 6.5 rx status register (06h) ................................................................................................... ........................... 18 6.6 receive overflow counter register (07h) .................................................................................... .............. 18 6.7 flow control register (0ah)................................................................................................ ......................... 18 6.8 eeprom & phy control register (0bh) ........................................................................................ ............. 18 6.9 eeprom & phy address register (0ch) ........................................................................................ ........... 19 6.10 eeprom & phy data registers (0dh~0eh)..................................................................................... ........ 19 6.11 link change control register (0fh) ........................................................................................ ................. 19 6.12 processor port physical address registers (10h~15h) ....................................................................... .. 19 6.13 processor port multicast address registers (16h~1dh)...................................................................... .. 19 6.14 rx packet length low register ( 20h ) ..................................................................................... ............... 20 6.15 rx packet length high register ( 21h ) .................................................................................... ............... 20 6.16 rx additional status register ( 26h ) ..................................................................................... .................. 20 6.17 rx additional control register ( 27h ).................................................................................... .................. 20 6.18 vendor id registers (28h~29h) ............................................................................................. .................... 20 6.19 chip revision register (2ch) .............................................................................................. ...................... 20 6.20 transmit check sum control register (31h) ................................................................................. .......... 20 6.21 receive check sum control status register (32h)........................................................................... ...... 21 6.22 up data bus driving capability register (38h) ............................................................................. ............ 21 6.23 irq pin control register (39h) ............................................................................................ ...................... 21 6.24 tx/rx memory size control register (3fh) .................................................................................. ........... 22 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 4 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 6.25 switch control register (52h)............................................................................................. ....................... 22 6.26 vlan control register (53h) ............................................................................................... ...................... 22 6.27 dsp phy control register (58h~59h)........................................................................................ ............... 23 6.28 per port control/status index register (60h).............................................................................. ............. 23 6.29 per port control data register (61h) ...................................................................................... .................. 23 6.30 per port status data register (62h) ....................................................................................... ................... 24 6.31 per port forward control register (65h) ................................................................................... ............... 24 6.32 per port ingress and egress control register (66h)........................................................................ ....... 25 6.33 per port bandwidth control setting register (67h) ......................................................................... ....... 26 6.34 per port block unicast ports control register (68h) . ...................................................................... ....... 27 6.35 per port block multicast ports control register (69h) ..................................................................... ...... 27 6.36 per port block broadcast ports control register (6ah)..................................................................... .... 27 6.37 per port block unknown ports control register (6bh) ....................................................................... ... 27 6.38 per port priority queue control register (6dh)............................................................................ ........... 27 6.39 per port vlan tag low byte register (6eh) ................................................................................. .......... 28 6.40 per port vlan tag high byte register (6fh)................................................................................ ........... 28 6.41 mib counter port index register (80h) ..................................................................................... ................ 28 6.42 mib counter data registers (81h~84h) ...................................................................................... .............. 28 6.43 port-based vlan mapping table registers (b0h~bfh)......................................................................... 29 6.44 tos priority map registers (c0h~cfh)...................................................................................... .............. 29 6.45 vlan priority map registers (d0h~d1h) ..................................................................................... ............ 32 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 5 DM9302-15-ds-p01 july 30, 2009 6.46 memory data pre-fetch read command without address increment register (f0h) ........................ 32 6.47 memory data read command with address increment re gister (f2h)................................................ 32 6.48 memory data read address register (f4h) ................................................................................... .......... 32 6.49 memory data read address register (f5h) ................................................................................... .......... 32 6.50 memory data write command without address increment register (f6h).......................................... 32 6.51 memory data write command with address increment register (f8h) ............................................... 33 6.52 memory data write address register (fah) .................................................................................. .......... 33 6.53 memory data write address register (fbh) .................................................................................. .......... 33 6.54 tx packet length registers (fch~fdh) ...................................................................................... ............ 33 6.55 interrupt status register (feh)........................................................................................... ....................... 33 6.56 interrupt mask register (ffh)............................................................................................. ....................... 33 7. eeprom format........... ............... ............... ............. ............. ............. ............. ........... 34 8. phy registers .......................................................................................................... 37 8.1 basic mode control register (bmcr) ? 00h ................................................................................... ........... 38 8.2 basic mode status register (bmsr) ? 01h .................................................................................... ............ 39 8.3 phy id identifier register #1 (phyid1) ? 02h............................................................................... .............. 40 8.4 phy id identifier register #2 (phyid2) ? 03h............................................................................... .............. 40 8.5 auto-negotiation advertisement register (anar) ? 04h....................................................................... ... 40 8.6 auto-negotiation link partner ability register (anlpar) ? 05h ............................................................. 4 1 8.7 auto-negotiation expansion register (aner) - 06h ........................................................................... ...... 42 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 6 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 8.8 davicom specified configuration register (dscr) ? 10h ...................................................................... 43 8.9 davicom specified configuration and status register (dscsr) ? 11h ................................................ 44 8.10 10base-t configuration/status (10btcsr) ? 12h............................................................................. ..... 45 8.11 power down control register (pwdor) ? 13h................................................................................. ....... 45 8.12 (specified config) register ? 14h ......................................................................................... ..................... 46 8.13 davicom specified receive error counter register (recr) ? 16h ..................................................... 47 8.14 davicom specified disconnect counter register (discr) ? 17h ........................................................ 47 8.15 power saving control register (pscr) ? 1dh ................................................................................ ......... 47 9. functional description....................................................................................... 48 9.1 processor bus and memory management function: .............................................................................. ... 48 9.1.1 processor interface ...................................................................................................... ............................ 48 9.1.2 direct memory access control............................................................................................. .................... 48 9.1.3 packet transmission...................................................................................................... .......................... 48 9.1.4 packet reception ......................................................................................................... ............................ 48 9.2 switch function:........................................................................................................... .................................. 49 9.2.1 address learning ......................................................................................................... ............................ 49 9.2.2 address aging ............................................................................................................ .............................. 49 9.2.3 packet forwarding ........................................................................................................ ........................... 49 9.2.4 inter-packet gap (ipg) ................................................................................................... ......................... 49 9.2.5 back-off algorithm....................................................................................................... ............................. 49 9.2.6 late collision........................................................................................................... ................................. 49 9.2.7 half duplex flow control ................................................................................................. ........................ 49 9.2.8 full duplex flow control ................................................................................................. ......................... 49 9.2.9 partition mode ........................................................................................................... ............................... 49 9.2.10 broadcast storm filtering............................................................................................... ........................ 50 9.2.11 bandwidth control....................................................................................................... ........................... 50 9.2.12 port monitoring support ................................................................................................. ........................ 50 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 7 DM9302-15-ds-p01 july 30, 2009 9.2.13 vlan support ............................................................................................................ ............................ 51 9.2.13.1 port-based vlan....................................................................................................... ......................... 51 9.2.13.2 802.1q-based vlan..................................................................................................... ...................... 51 9.2.13.3 tag/untag ............................................................................................................. .............................. 51 9.2.14 priority support ........................................................................................................ .............................. 51 9.2.14.1 port-based priority ................................................................................................... ........................... 52 9.2.14.2 802.1p-based priority................................................................................................. ......................... 52 9.2.14.3 diffserv-based priority............................................................................................... ......................... 52 9.3 internal phy functions ..................................................................................................... ............................. 53 9.3.1 100base-tx operation ..................................................................................................... ....................... 53 9.3.1.1 4b5b encoder ........................................................................................................... ............................ 53 9.3.1.2 scrambler .............................................................................................................. ................................ 53 9.3.1.3 parallel to serial converter ........................................................................................... ........................ 53 9.3.1.4 nrz to nrzi encoder .................................................................................................... ....................... 53 9.3.1.5 mlt-3 converter ........................................................................................................ ........................... 53 9.3.1.6 mlt-3 driver ........................................................................................................... .............................. 53 9.3.1.7 4b5b code group........................................................................................................ ......................... 54 9.3.2 100base-tx receiver ...................................................................................................... ........................ 55 9.3.2.1 signal detect .......................................................................................................... ............................... 55 9.3.2.2 adaptive equalization.................................................................................................. .......................... 55 9.3.2.3 mlt-3 to nrzi decoder.................................................................................................. ...................... 55 9.3.2.4 clock recovery module .................................................................................................. ...................... 55 9.3.2.5 nrzi to nrz ............................................................................................................ ............................. 55 9.3.2.6 serial to parallel ..................................................................................................... ............................... 55 9.3.2.7 descrambler ............................................................................................................ .............................. 55 9.3.2.8 code group alignment................................................................................................... ....................... 56 9.3.2.9 4b5b decoder........................................................................................................... ............................ 56 9.3.3 10base-t operation....................................................................................................... .......................... 56 9.3.4 collision detection ...................................................................................................... ............................. 56 9.3.5 carrier sense ............................................................................................................ ............................... 56 9.3.6 auto-negotiation ......................................................................................................... ............................. 56 10. dc and ac electrical characteristics ..................................................... 57 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 8 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 10.1 absolute maximum ratings .................................................................................................. ..................... 57 10.2 operating conditions...................................................................................................... ............................ 57 10.3 dc electrical characteristics ............................................................................................. ........................ 58 10.4 ac characteristics ........................................................................................................ ............................... 59 10.4.1 power on reset timing ................................................................................................... ...................... 59 10.4.2 processor i/o read timing............................................................................................... ..................... 60 10.4.3 processor i/o write timing .............................................................................................. ...................... 61 10.4.4 eeprom timing ........................................................................................................... .......................... 62 11. package information........................................................................................ 63 12. ordering information ...................................................................................... 64 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 9 DM9302-15-ds-p01 july 30, 2009 1. general description the DM9302 fiber converter is complied with ieee802.3 standards, and designed to convert data signal between 10/100 base-tx and 100 base-fx fast ethernet. media converters are connected between fiber cable and twisted cable segments with network and also the simplest way to interconnect any equipment?s 100base-tx / 10base-t to the 100base-fx interface network. 2. block diagram 100m pecl txmt/ rxcr 100m mac 10 / 100 m phy 10 / 100 m mac port 0 pecl tx/rx port 1 mdi / mdix switch controller control registers mib counters eeprom interface embedded memory memory bist memory management processor interface host mac switch engine 8 / 16 bit processor bus eeprom switch fabric DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 10 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 3. features ? 10/100base-tx/fx switch base single-chip media converter ? compliant with ieee802.3u 100base-tx standard, compliant with ansi x3t12 tp-pmd 1995 standard, compliant with ansi x3.166 fddi-pmd ? 8/16-bit processor interface ? per port supports 4 priority queues by port-based, 802.1p vlan, and ip tos priority. ? support 802.1q vlan up-to 16 vlan group ? support vlan id tag/untag options ? per port support bandwidth, ingress and egress rate control ? support broadcast storming filter function ? support store and forward switching approach ? support ieee 802.3x flow control in full-duplex mode ? support back pressure flow control in half-duplex mode ? recode up-to 1k uni-cast mac addresses ? automatic aging scheme ? eeprom interface for power up configurations ? support mib-ii counters ? local bus slave architecture ? tcp/ip/udp/ipv4 checksum offload ? compatible with 3.3v and 5.0v tolerant i/o ? dsp phy with hp auto-mdix, ds p architecture phy transceiver ? 64-pin lqfp, 0.18 um process, support lead-free and halogen?free DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 11 DM9302-15-ds-p01 july 30, 2009 4. pin configuration : 64 pin lqfp 11 32 31 30 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 29 28 27 26 25 vref gnd x2 gnd vcc3 lnk0_led spd0_led test2 cmd cs# iow# gnd vcc3 ior# sd7 irq sd1 sd4 vcci vcc3 sd6 gnd sd2 sd13 vcntl test1 gnd sd15 sd14 eedio pwrst# vcc3 sd12 sd9 sd8 eecs gnd sd0 eeck sd10 49 50 51 52 53 54 55 56 57 58 59 60 61 63 64 62 vcci spd1_led x1 lnk1_led sd11 sd3 sd5 gnd 36 37 38 39 40 41 42 43 44 45 46 33 34 35 48 47 avddi tx1+ tx1- agnd rx1+ rx1- avdd3 avddi tx0+ tx0- agnd rx0+ rx0- avdd3 bgres sd DM9302 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 12 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 5. pin description i = input, o = output, i/o = input / output, o/d = open dr ain, p = power, pd=internal pull-low (approx. 50k ohm) # = asserted low 5.1 processor bus interface pin no. pin name i/o description 2 ior# i processor read command default is low active. the polarity can be changed by setting eeprom. 3 irq o interrupt request default is high active and non-open collector type. its polarity and output type can be changed by strap pins or eeprom setting. 5,6,7,9,10,12,14,15, 17,18,19,20,21,22,24,25 sd0~15 i/o processor data bus bit 0~15 60 cmd i command type upon the io transaction, when cmd is high, sd0~15 reflect the value of data port when cmd is low, sd0~15 reflect the value of index port 62 cs# i processor chip select command default is low active. its polarity can be changed by eeprom setting. 63 iow# i processor write command default is low active. its polarity can be changed by eeprom setting. 5.2 eeprom interfaces pin no. pin name i/o description 27 eedio i,/o eeprom data in/out 28 eeck o,pd eeprom serial clock this pin is used as the clock for the eeprom data transfer. 29 eecs o,pd eeprom chip selection. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 13 DM9302-15-ds-p01 july 30, 2009 5.3 led pins pin no. pin name i/o description 55 lnk1_led o/d port 1 link / active led it is the combined led of link and carrier sense signal of the port 1. 56 spd1_led o/d port 1 speed led it?s low to indicate that the port 1 operates in 100m mode. it?s floating to indicate that the port 1 operates in 10m mode. 57 lnk0_led o/d port 0 link / active led it is the combined led of link and carrier sense signal of the port 0. 58 spd0_led o/d port 0 speed led it?s low to indicate that the port 0 operates in 100m mode. it?s floating to indicate that the port 0 operates in 10m mode. 5.4 clock interface pin no. pin name i/o description 52 x1 i crystal 25mhz in 53 x2 o crystal 25mhz out 5.5 network interface pin no. pin name i/o description 34,35 tx1+/- i/o port 1 tp tx these two pins are the transmit output in mdi mode or the receive input in mdix mode. 37,38 rx1+/- i/o port 1 tp rx these two pins are the receive input in mdi mode or the transmit output in mdix mode. 41,42 tx0+/- i/o port 0 fx tx fiber transmitter data pair. 44,45 rx0+/- i/o port 0 fx rx fiber receiver data pair. 47 bgres i/o band gap pin connect a 1.4kohm 1% resistor to analog ground (agnd) in application. 48 sd i fiber signal detect 49 vcntl i/o 1.8v voltage control 50 vref o voltage reference connect a 0.1uf capacitor to ground in application. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 14 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 5.6 miscellaneous pins pin no. pin name i/o description 30 pwrst# i power-on reset low active with minimum 1ms 32 test1 i,pd tie to ground in application 59 test2 i,pd tie to ground in application 5.7 power pins pin no. pin name i/o description 1,13,26,51 vcc3 p digital 3.3v 11,61 vcci p internal 1.8v core power 4,8,16,23,31,54,64 gnd p digital gnd 39,46 avdd3 p analog 3.3v power 33,40 avddi p analog 1.8v power 36,43 agnd p analog gnd 5.8 strap pins table 1: pull-high 1k~10k, 0: floating (default).,. pin no. pin name description 28 eeck processor data bus width 0: 16-bit, sd 0-15 is used as processor data bus (default) 1: 8-bit, sd 0-7 is used as processor data bus; sd 8-15 is left floating. 29 eecs polarity of irq 0: irq pin high active (default) 1: irq pin low active DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 15 DM9302-15-ds-p01 july 30, 2009 6. control and status register set the DM9302 implements several control and status registers (csr), which can be accessed by the host. all csr are set to their default values by power on or software reset unless specified. register description offset default value after reset ncr network control register 00h 00h nsr network status register 01h 00h tcr tx control register 02h 00h rcr rx control register 05h 00h rsr rx status register 06h 00h rocr receive overflow counter register 07h 00h fcr flow control register 0ah 00h epcr eeprom & phy control register 0bh 00h epar eeprom & phy address register 0ch 40h epdrl eeprom & phy low byte data register 0dh 00h epdrh eeprom & phy high byte data register 0eh 00h lccr link change control register (0fh) 0fh 00h par processor port physical address registers 10h-15h by eeprom mar processor port multicast address registers 16h-1dh xxh rxpllr rx packet length low register 20h 00h rxplhr rx packet length high register 21h 00h rasr rx additional status register 26h 00h racr rx additional control register 27h 00h vid vendor id registers 28h-29h 0a46h chipr chip revision registers 2ch 01h tcscr transmit check sum control register 31h 00h rcscsr receive check sum control status register 32h 00h driver up data bus driving capability register 38h 00h irqcr irq pin control register 39h 00h switchcr switch control register 52h 00h vlancr vlan control register 53h 00h dsp1,2 dsp control register i,ii 58h~59h 0000h p_index per port control/status index register 60h 00h p_ctrl per port control data register 61h 00h p_stus per port status data register 62h 00h p_rate per port ingress and egress rate control register 66h 00h p_bw per port bandwidth control setting register 67h 00h p_unicast per port block unicast ports control register 68h 00h p_multi per port block multicast ports control register 69h 00h p_bcast per port block broadcast ports control register 6ah 00h p_unknwn per port block unknown ports control register 6bh 00h p_pri per port priority queue control register 6dh 00h vlan_tagl per port vlan tag low byte register 6eh 01h vlan_tagh per port vlan tag high byte register 6fh 00h p_mib_idx per port mib counter index register 80h 00h mib_dat mib counter data register bit 0~7 81h 00h DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 16 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 mib counter data register bit 8~15 82h 00h mib counter data register bit 16~23 83h 00h mib counter data register bit 24~31 84h 00h pvlan port-based vlan mapping table registers b0-bfh 0fh tos_map tos priority map registers c0-cfh 00h~ffh vlan_map vlan priority map registers d0-d1h 50h,fah mrcmdx memory data pre-fetch read command without address increment register f0h xxh mrcmd memory data read command with address increment register f2h xxh mrrl memory data read_ address register low byte f4h 00h mrrh memory data read_ address register high byte f5h 00h mwcmdx memory data write command without address increment register f6h xxh mwcmd memory data write command with address increment register f8h xxh mwrl memory data write_ address register low byte fah 00h mwrh memory data write _ address register high byte fbh 00h txpll tx packet length low byte register fch xxh txplh tx packet length high byte register fdh xxh isr interrupt status register feh 00h imr interrupt mask register ffh 00h DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 17 DM9302-15-ds-p01 july 30, 2009 key to default in the register description that follows, the default column takes the form: DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 18 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 6.3 tx control register (02h) bit name default description 7:4 reserved 0,ro reserved 3 crc_dis2 phs0,rw crc appends disable for packet index 2 2 reserved 0,ro reserved 1 crc_dis1 phs0,rw crc appends disable for packet index 1 0 txreq phs0,rw tx request. auto clears after transmit completely 6.4 rx control register (05h) bit name default description 7 hashall phs0,rw filter all address in hash table 6 reserved phs0,rw reserved 5:4 reserved phs0,rw reserved 3 all phs0,rw pass all multicast packets all received packets with bit 0 is ?1? of destination address (da) field are accepted and save to receive memory. 2 reserved phs0,rw reserved 1 prmsc phs0,rw promiscuous mode all received packets are accepted and save to receive memory without da field filter. 0 rxen phs0,rw rx enable 6.5 rx status register (06h) bit name default description 7:4 reserved 0,ro reserved 3:2 srcp 0,ro source port number 1 ce ph0,ro crc error it is set to indicate that the rece ived frame ends with a crc error 0 reserved 0,ro reserved 6.6 receive overflow counter register (07h) bit name default description 7 rxfu phs0,r/c receive overflow counter overflow this bit is set when the roc has an overflow condition 6:0 roc phs0,r/c receive overflow counter this is a statistic counter to indicate the received packet count upon fifo overflow 6.7 flow control register (0ah) bit name default description 7:6 reserved 0,ro reserved 5 flow_en phs0,rw rx flow control enable enables the pause packet for high/low water threshold control 4:0 reserved 0,ro reserved 6.8 eeprom & phy control register (0bh) bit name default description 7:6 reserved 0,ro reserved 5 reep ph0,rw reload eeprom. driver needs to clear it up after the operation completes 4 wep ph0,rw write eeprom enable DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 19 DM9302-15-ds-p01 july 30, 2009 3 epos ph0,rw eeprom or phy operation select when reset, select eeprom; when set, select phy 2 erprr ph0,rw eeprom read or phy register read command. driver needs to clear it up after the operation completes. 1 erprw ph0,rw eeprom write or phy register write command. driver needs to clear it up after the operation completes. 0 erre ph0,ro eeprom access status or phy access status when set, it indicates that the eeprom or phy access is in progress 6.9 eeprom & phy address register (0ch) bit name default description 7:6 phy_adr ph01,rw phy address bit 1 and 0; the phy address bit [4:2] is force to 0. 5:0 eroa ph0,rw eeprom word address or phy register address 6.10 eeprom & phy data registers (0dh~0eh) bit name default description 7:0 epdrl ph0,rw eeprom or phy low byte data (0dh) this data is made to write/read low byte of word address defined in reg. 0ch to eeprom or phy 7:0 epdrh ph0,rw eeprom or phy high byte data (0eh) this data is made to write/read high byte of word address defined in reg. 0ch to eeprom or phy 6.11 link change control register (0fh) bit name type description 7:6 reserved 0,ro reserved 5 linken pe0,rw link change event enable when both set of this bit and bit 6 of ncr, it enables link change status event 4:3 reserved 0,ro reserved 2 linkst ph0,ro link change event status when set, it indicates that link status change event (link of port 0 or 1) occurred this bit can be cleared by write 1 to bit 5 of nsr or write 0 to bit 6 of ncr. 1:0 reserved 0,ro reserved 6.12 processor port physical address registers (10h~15h) bit name default description 7:0 pab5 e,rw physical address byte 5 (15h) 7:0 pab4 e,rw physical address byte 4 (14h) 7:0 pab3 e,rw physical address byte 3 (13h) 7:0 pab2 e,rw physical address byte 2 (12h) 7:0 pab1 e,rw physical address byte 1 (11h) 7:0 pab0 e,rw physical address byte 0 (10h) 6.13 processor port multicast address registers (16h~1dh) bit name default description 7:0 mab7 x,rw multicast address byte 7 (1dh) 7:0 mab6 x,rw multicast address byte 6 (1ch) 7:0 mab5 x,rw multicast address byte 5 (1bh) DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 20 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 7:0 mab4 x,rw multicast address byte 4 (1ah) 7:0 mab3 x,rw multicast address byte 3 (19h) 7:0 mab2 x,rw multicast address byte 2 (18h) 7:0 mab1 x,rw multicast address byte 1 (17h) 7:0 mab0 x,rw multicast address byte 0 (16h) 6.14 rx packet length low register ( 20h ) bit name default description 7:0 rxpll ph,ro rx packet length low byte 6.15 rx packet length high register ( 21h ) bit name default description 7:0 rxplh ph,ro rx packet length high byte 6.16 rx additional status register ( 26h ) bit name default description 7:4 reserved 0,ro reserved 1:0 rptrs ph,ro up received pointer status, only available when rx pointer restriction is enabled (reg27h.7=0). 00: within buffer 01: end of buffer 1x: exceed buffer 6.17 rx additional control register ( 27h ) bit name default description 7 rprd phs0,rw rx pointer restriction disable 6:0 reserved 0,ro reserved 6.18 vendor id registers (28h~29h) bit name default description 7:0 vidh pe,0ah,ro vendor id high byte (29h) 7:0 vidl pe,46h.ro vendor id low byte (28h) 6.19 chip revision register (2ch) bit name default description 7:0 chipr 01h,ro chip revision 6.20 transmit check sum control register (31h) bit name default description 7~3 reserved 0,ro reserved 2 udpcse hp0,rw udp checksum generation enable 1 tcpcse hp0,rw tcp checksum generation enable 0 ipcse hp0,rw ip checksum generation enable DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 21 DM9302-15-ds-p01 july 30, 2009 6.21 receive check sum control status register (32h) bit name default description 7 udps hp0,ro udp checksum status 1: udp packet checksum is fail. 0: udp packet checksum is ok or it is not a udp packet. 6 tcps hp0,ro tcp checksum status 1: tcp packet checksum is fail. 0: tcp packet checksum is ok or it is not a tcp packet. 5 ips hp0,ro ip checksum status 1: ip packet checksum is ail 0: ip packet checksum is ok or it is not an ip packet. 4 udpp hp0,ro this is an udp packet 3 tcpp hp0,ro this is a tcp packet 2 ipp hp0,ro this is an ip packet 1 rcsen hps0,rw receive checksum checking enable when set, the checksum status will store in packet first byte of status header. 0 dcse hps0,rw discard checksum error packet when set, ip/tcp/udp checksum field is error, this packet will be discarded. 6.22 up data bus driving capability register (38h) bit name default description 7 reserved 0,rw reserved 6:5 isa_curr p01,rw sd bus current driving/sinking capability 00: 2ma 01: 4ma (default) 10: 6ma 11: 8ma 4:3 reserved p0,rw reserved 2 step p0,rw data bus output stepping 1: disabled 0: enabled 1 iow_spike p0,rw eliminate iow spike 1: eliminate about 2ns iow spike 0 ior_spike p1,rw eliminate ior spike 1: eliminate about 2ns ior spike 6.23 irq pin control register (39h) bit name default description 7:2 reserved ps0,ro reserved 1 irq_type pet0,rw irq pin output type control 1: irq open-collector output 0: irq direct output 0 irq_pol pet0,rw irq pin polarity control 1: irq active low 0: irq active high DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 22 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 6.24 tx/rx memory size control register (3fh) bit name default description 7:6 reserved ps0,ro reserved 5:0 tx_size p20h,rw tx block size in 2-port mode this value defines the transmit block size in 256-byte unit. tx memory size = tx_size * 256 bytes and then rx memory size = 16kb ? (tx_size + 1)*256-byte note: the value of tx_size should be between 14h and 30h 6.25 switch control register (52h) bit name default description 7 mem_bist ph0,ro address memory test bist status 0: ok 1: fail 6 rst_sw p0,rw reset switch core and auto clear after 10us 5 rst_anlg p0,rw reset analog phy core and auto clear after 10us 4:3 snf_port pe00,rw sniffer port number define the port number to act as the sniffer port 2 crc_dis pe0,rw crc checking disable when set, the received crc error packet also accepts to receive memory. 1:0 age pe0,rw aging 00: no aging 01: 64 32 sec 10: 128 64 sec 11: 256 128 sec 6.26 vlan control register (53h) bit name default description 7 tos6 pe0,rw full tos using enable 1: check most significant 6-bit of tos 0: check most significant 3-bit only of tos 6 reserved 0,ro reserved 5 unicast pe0,rw unicast packet can across vlan boundary 4 vidff pe0,rw replace vidff if the received packet is a tagged vlan with vid equal to ?fff?, its vlan field is replaced with vlan tag defined in reg. 6eh and 6fh. 3 vid1 pe0,rw replace vid01 if the received packet is a tagged vlan with vid equal to ?001?, its vlan field is replaced with vlan tag defined in reg. 6eh and 6fh. 2 vid0 pe0,rw replace vid0 if the received packet is a tagged vlan with vid equal to ?000?, its vlan field is replaced with vlan tag defined in reg. 6eh and 6fh. 1 pri pe0,rw replace priority field in the tag with value define in reg 6fh bit 7~5. 0 vlan pe0,rw vlan mode enable 1: 802.1q base vlan mode enable 0: port-base vlan only DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 23 DM9302-15-ds-p01 july 30, 2009 6.27 dsp phy control register (58h~59h) 58h: bit name default description 7:0 dsp_ctl1 0,rw dsp control register 1 for testing only (register 58h) 59h: bit name default description 7:0 dsp_ctl2 0,rw dsp control register 2 for testing only (register 59h) 6.28 per port control/status index register (60h) bit name default description 7:5 reserved phs0,rw reserved 4:2 reserved 0,ro reserved 1:0 index phs0,rw port index for register 61h~84h write the port number to this register before write/read register 61h~84h. note: the processor port index number is 3 6.29 per port control data register (61h) bit name default description 7 reserved pe0,rw reserved 6 parti_en pe0,rw enable partition detection 5 no_dis_rx pe0,rw not discard rx packets when ingress bandwidth control when received packets bandwidth reach ingress bandwidth threshold, the packets over the threshold are not discarded but with flow control. 4 flow_dis pe0,rw flow control in full duplex mode, or back pressure in half duplex mode enable 0: enable 1: disable 3 bandwidth pe0,rw bandwidth control 0: control with ingress and egress separately, ref to register 66h. 1: control with ingress or egress, ref to register 67h 2 bp_dis pe0,rw broadcast packet filter 0: accept broadcast packets 1: reject broadcast packets 1 mp_dis pe0,rw multicast packet filter 0: accept multicast packets 1: reject multicast packets 0 mp_storm pe0,rw broadcast storm control 0: only broadcast packets storm are controlled 1: multicast packets also same as broadcast storm control. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 24 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 6.30 per port status data register (62h) bit name default description 7:6 reserved p0,ro reserved 5 lp_fcs p0,ro link partner flow control enable status 4 bist p0,ro bist status 1: sram bist fail 0: sram bist pass 3 reserved 0,ro reserved 2 speed2 p0,ro phy speed status 0: 10mbps, 1: 100mbps 1 fdx2 p0,ro phy duplex status 0: half-duplex, 1: full-duplex 0 link2 p0,ro phy link status 0: link fail, 1: link ok 6.31 per port forward control register (65h) bit name default description 7 loopback ph0,rw loop-back mode the received packet will be forward to this port itself. 6 moni_tx ph0,rw tx packet monitored the transmitted packets are also forward to sniffer port. 5 moni_rx ph0,rw rx packet monitored the received packets are also forward to sniffer port. 4 dis_bmp ph0,rw broad/multicast not monitored the received broadcast or multicast packets are not forward to sniffer port. 3 reserved ph0,rw reserved 2 tx_dis ph0,rw packet transmit disabled all packets can not be forward to this port. 1 rx_dis ph0,rw packet receive disabled all received packets are discarded. 0 adr_dis ph0,rw address learning disabled the source address (sa) field of packet is not learned to address table. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 25 DM9302-15-ds-p01 july 30, 2009 6.32 per port ingress and egress control register (66h) bit name default description 7:4 ingress pe0,rw ingress rate control these bits define the bandwidth threshold that received packets over the threshold are discarded. ingress rate table below 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps 3:0 egress pe0,rw egress rate control these bits define the bandwidth threshold that transmitted packets over the threshold are discarded. egress rate table below 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 26 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 6.33 per port bandwidth control setting register (67h) bit name default description 7:4 bsth pe0,rw broadcast storm threshold these bits define the bandwidth threshold that received broadcast packets over the threshold are discarded. threshold table below 0000: no broadcast storm control 0001: 8k packets/sec 0010: 16k packets/sec 0011: 64k packets/sec 0100: 5% 0101: 10% 0110: 20% 0111: 30% 1000: 40% 1001: 50% 1010: 60% 1011: 70% 1100: 80% 1101: 90% 111x: no broadcast storm control 3:0 bw ctrl pe0,rw received packet length counted. bandwidth table below these bits define the bandwidth threshold that transmitted or received packets over the threshold are discarded. bandwidth table below 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 27 DM9302-15-ds-p01 july 30, 2009 6.34 per port block unicast ports control register (68h) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_up ph0,rw ports of unicast packet be blocked the received unicast packets are not forward to the assigned ports. note: that the assigned port definition: bit 0 for port 0, bit 1 for port 1, bit 2 reserved, and bit 3 for processor port. 6.35 per port block multicast ports control register (69h) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_mp ph0,rw ports of multicast packet be blocked the received multicast packets are not forward to the assigned ports. 6.36 per port block broadcast ports control register (6ah) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_bp ph0,rw ports of broadcast packet be blocked the received broadcast packets are not forward to the assigned ports. 6.37 per port block unknown ports control register (6bh) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_ukp ph0,rw ports of unknown packet be blocked the packets with da field not found in address table are not forward to the assigned ports. 6.38 per port priority queue control register (6dh) bit name default description 7 tag_out pe0,rw output packet tagging enable the transmitted packets are containing vlan tagged field. 6 pri_dis pe0,rw priority queue disable only one transmit queue is supported in this port. 5 wfque pe0,rw weighted round-robin queuing 1: the priority weight for queue 3, 2, 1, and 0 is 8, 4, 2, and 1 respectively. 0: the queue 3 has the highest priority, and the next priorities are queue 2, 1, and 0 respectively. 4 tos_pri pe0,rw priority tos over vlan if an ip packet with vlan tag, the priority of this packet is decode from tos field. 3 tos_off pe0,rw tos priority classification disable the priority information from tos field of ip packet is ignored. 2 pri_off pe0,rw 802.1 p priority classification disable the priority information from vlan tag field is ignored. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 28 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 1:0 p_pri pe0,rw port base priority the priority queue number in port base. 00 : queue 0, 01 : queue 1, 10 : queue 2, 11 : queue 3 6.39 per port vlan tag low byte register (6eh) bit name default description 7:0 vid70 pe01,rw vid[7:0] 6.40 per port vlan tag high byte register (6fh) bit name default description 7:5 pri pe0,rw tag [15:13] 4 cfi pe0,rw tag[12] 3:0 vid118 pe0,rw vid[11:8] 6.41 mib counter port index register (80h) bit name default description 7 ready p0,ro mib counter data is ready when this register is written with index data, this bit is cleared and the mib counter reading is in progress. after end of read mib counter, the mib data is loaded into registers 81h~ 84h and this bit is set to indicate that the mib data is ready, and then the mib data of this index is cleared. 6:5 reserved 0,ro reserved 4:0 index phs0,rw mib counter index 0~9, each counter is 32-bit in register 81h~84h. write the mib counter index to this register before read them. 6.42 mib counter data registers (81h~84h) register name default description 81h mib_dat x,ro mib counter data register bit 0~7 82h mib_dat x,ro mib counter data register bit 8~15 83h mib_dat x,ro mib counter data register bit 16~23 84h mib_dat x,ro mib counter data register bit 24~31 mib counter: rx byte counter registers (index 00h) mib counter: rx uni-cast packet counter registers (index 01h) mib counter: rx multi-cast packet counter registers (index 02h) mib counter: rx discard packet counter registers (index 03h) mib counter: rx error packet counter registers (index 04h) mib counter: tx byte counter registers (index 05h) mib counter: tx uni-cast packet counter registers (index 06h) mib counter: tx multi-cast packet counter registers (index 07h) mib counter: tx discard packet counter registers (index 08h) mib counter: tx error packet counter registers (index 09h) DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 29 DM9302-15-ds-p01 july 30, 2009 6.43 port-based vlan mapping table registers (b0h~bfh) define the port member in vlan group there are 16 vlan group that defined in reg. b0h~bfh. group 0 defined in reg. b0h, and group 1 defined in reg. b1h, and so on. bit name default description 7:4 reserved pe0,ro reserved 3 port_up pe1,rw mapping to processor 2 reserved pe1,rw reserved 1 port_p1 pe1,rw mapping to port 1 0 port_p0 pe1,rw mapping to port 0 6.44 tos priority map registers (c0h~cfh) define the 6-bit or 3-bit of tos field mapping to 2-bit priority queue number. in 6-bit type, the reg. 53h bit 7 is ?1?, reg. c0h bit [1:0] de fine the mapping for tos value 0, reg. 60h bit [3:2] define the mapping for tos value 1, and so on, till reg. cfh bit [7:6] define tos value 63. in 3-bit type, reg. 53h bit 7 is ?0? define the mapping for tos value 0, reg. 60h bit [3:2] define the mapping for tos value 1, and so on, till reg. c1h bit [7:6] define tos value 7. reg. c0h: bit name default description 7:6 tos3 pe0/1,rw if reg. 53h. bit 7 =1 :tos[7:2]=03h, otherwise tos]7:5]=03h 5:4 tos2 pe0,/1rw if reg. 53h. bit 7 =1 :tos[7:2]=02h, otherwise tos]7:5]=02h 3:2 tos1 pe0,rw if reg.53h. bit 7 =1 :tos[7:2]=01h, otherwise tos]7:5]=01h 1:0 tos0 pe0,rw if reg.53h. bit 7 =1 :tos[7:2]=00h, otherwise tos]7:5]=00h reg. c1h: bit name default description 7:6 tos7 pe0/3,rw if reg.53h. bit 7=1 :tos[7:2]=07h, otherwise tos]7:5]=07h 5:4 tos6 pe0/3,rw if reg.53h. bit 7=1 :tos[7:2]=06h, otherwise tos]7:5]=06h 3:2 tos5 pe0/2,rw if reg.53h. bit 7=1 :tos[7:2]=05h, otherwise tos]7:5]=05h 1:0 tos4 pe0/2,rw if reg.53h. bit 7=1 :tos[7:2]=04h, otherwise tos]7:5]=04h reg. c2h: bit name default description 7:6 tosb pe0,rw if reg.53h. bit 7=1 :tos[7:2]=0bh 5:4 tosa pe0,rw if reg.53h. bit 7=1 :tos[7:2]=0ah 3:2 tos9 pe0,rw if reg.53h. bit 7=1 :tos[7:2]=09h 1:0 tos8 pe0,rw if reg.53h. bit 7=1 :tos[7:2]=08h reg. c3h: bit name default description 7:6 tosf pe0,rw if reg.53h. bit 7=1 :tos[7:2]=0fh 5:4 tose pe0,rw if reg.53h. bit 7=1 :tos[7:2]=0eh 3:2 tosd pe0,rw if reg.53h. bit 7=1 :tos[7:2]=0dh 1:0 tosc pe0,rw if reg.53h. bit 7=1 :tos[7:2]=0ch DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 30 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 reg. c4h: bit name default description 7:6 tos13 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=13h 5:4 tos12 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=12h 3:2 tos11 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=11h 1:0 tos10 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=10h reg. c5h: bit name default description 7:6 tos17 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=17h 5:4 tos16 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=16h 3:2 tos15 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=15h 1:0 tos14 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=14h reg. c6h: bit name default description 7:6 tos1b pe1,rw if reg.53h. bit 7=1 :tos[7:2]=1bh 5:4 tos1a pe1,rw if reg.53h. bit 7=1 :tos[7:2]=1ah 3:2 tos19 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=19h 1:0 tos18 pe1,rw if reg.53h. bit 7=1 :tos[7:2]=18h reg. c7h: bit name default description 7:6 tos1f pe1,rw if reg.53h. bit 7=1 :tos[7:2]=1fh 5:4 tos1e pe1,rw if reg.53h. bit 7=1 :tos[7:2]=1eh 3:2 tos1d pe1,rw if reg.53h. bit 7=1 :tos[7:2]=1dh 1:0 tos1c pe1,rw if reg.53h. bit 7=1 :tos[7:2]=1ch reg. c8h: bit name default description 7:6 tos23 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=23h 5:4 tos22 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=22h 3:2 tos21 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=21h 1:0 tos20 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=20h reg. c9h: bit name default description 7:6 tos27 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=27h 5:4 tos26 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=26h 3:2 tos25 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=25h 1:0 tos24 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=24h DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 31 DM9302-15-ds-p01 july 30, 2009 reg. cah: bit name default description 7:6 tos2b pe2,rw if reg.53h. bit 7=1 :tos[7:2]=2bh 5:4 tos2a pe2,rw if reg.53h. bit 7=1 :tos[7:2]=2ah 3:2 tos29 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=29h 1:0 tos28 pe2,rw if reg.53h. bit 7=1 :tos[7:2]=28h reg. cbh: bit name default description 7:6 tos2f pe2,rw if reg.53h. bit 7=1 :tos[7:2]=2fh 5:4 tos2e pe2,rw if reg.53h. bit 7=1 :tos[7:2]=2eh 3:2 tos2d pe2,rw if reg.53h. bit 7 =1 :tos[7:2]=2dh 1:0 tos2c pe2,rw if reg.53h. bit 7 =1 :tos[7:2]=2ch reg. cch: bit name default description 7:6 tos33 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=33h 5:4 tos32 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=32h 3:2 tos31 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=31h 1:0 tos30 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=30h reg. cdh: bit name default description 7:6 tos37 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=37h 5:4 tos36 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=36h 3:2 tos35 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=35h 1:0 tos34 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=34h reg. ceh: bit name default description 7:6 tos3b pe3,rw if reg.53h. bit 7=1 :tos[7:2]=3bh 5:4 tos3a pe3,rw if reg.53h. bit 7=1 :tos[7:2]=3ah 3:2 tos39 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=39h 1:0 tos38 pe3,rw if reg.53h. bit 7=1 :tos[7:2]=38h reg. cfh: bit name default description 7:6 tos3f pe3,rw if reg.53h. bit 7=1 :tos[7:2]=3fh 5:4 tos3e pe3,rw if reg.53h. bit 7=1 :tos[7:2]=3eh 3:2 tos3d pe3,rw if reg.53h. bit 7=1 :tos[7:2]=3dh 1:0 tos3c pe3,rw if reg.53h. bit 7 =1 :tos[7:2]=3ch DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 32 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 6.45 vlan priority map registers (d0h~d1h) define the 3-bit of priority field valn mapping to 2-bit priority queue number. reg. d0h: bit name default description 7:6 tag3 pe1,rw vlan priority tag value = 03h 5:4 tag2 pe1,rw vlan priority tag value = 02h 3:2 tag1 pe0,rw vlan priority tag value = 01h 1:0 tag0 pe0,rw vlan priority tag value = 00h reg. d1h: bit name default description 7:6 tag7 pe3,rw vlan priority tag value = 07h 5:4 tag6 pe3,rw vlan priority tag value = 06h 3:2 tag5 pe2,rw vlan priority tag value = 05h 1:0 tag4 pe2,rw vlan priority tag value = 04h 6.46 memory data pre-fetch read command without address increment register (f0h) bit name default description 7:0 mrcmdx x,ro read data from rx sram. after the read of this command, the read pointer of internal sram is unchanged. and the DM9302 starts to pre-fetch the sram data to internal data buffers. 6.47 memory data read command with address increment register (f2h) when register ffh bit 7 is ?0?, register f5h value will be returned to 0000h, if 16k-byte boundary is reached. when register ffh bit 7 is ?1?, register f5h value will be returned to 0000h, if processor port receive memory byte boundary address rx memory size, defined in register 3fh with default 1f00h, is reached. bit name default description 7:0 mrcmd x,ro read data from rx sram. after the read of this command, the read pointer is increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit respectively) 6.48 memory data read address register (f4h) when register ffh bit 7 is ?0?, register f5h and f4h can be us ed as memory byte address to read internal 64k-byte memory. when register ffh bit 7 is ?1?, register f5h and f4h can be used as processor port receive memory byte address with memory space range from 0 to (rx memory size - 1), defined in register 3fh with default 1effh. bit name default description 7:0 mdral phs0,rw memory data read address low byte[7:0] 6.49 memory data read address register (f5h) bit name default description 7:0 mdrah50 phs0,rw memory data read byte address high byte[15:8] 6.50 memory data write command without address increment register (f6h) bit name default description 7:0 mwcmdx x,wo write data to tx sram. after the write of this command, the write pointer is unchanged DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 33 DM9302-15-ds-p01 july 30, 2009 6.51 memory data write command with address increment register (f8h) when register ffh bit 7 is ?0?, register fbh value will be returned to 0000h, if 16k-byte boundary is reached. bit name default description 7:0 mwcmd x,wo write data to tx sram after the write of this command, the write pointer is increased by 1, 2, or 4, depends on the operator mode. (8-bit, 16-bit,32-bit respectively) 6.52 memory data write address register (fah) when register ffh bit 7 is ?0?, register fbh and fah can be used as memory byte address to write internal 64k-byte memory. when register ffh bit 7 is ?1?, register fbh and fah are reserved. the processor port transmit memory address is generated by DM9302 automatically. bit name default description 7:0 mdwal phs0,rw memory data write_ address low byte[7:0] 6.53 memory data write address register (fbh) bit name default description 7:0 mdwah phs0,rw memory data write byte address high byte[15:8] 6.54 tx packet length registers (fch~fdh) bit name default description 7:0 txplh phs0,rw tx packet length high byte 7:0 txpll phs0,rw tx packet length low byte 6.55 interrupt status register (feh) bit name default description 7 iomode t0, ro width processor data bus 0: 16-bit mode 1: 8-bit mode 6 reserved phs0,ro reserved 5 lnkchg phs0,rw/c1 link status change of port 0 or 1 4 cnt_err phs0,rw/c1 memory management error 3 roo phs0,rw/c1 receive overflow counter overflow 2 ros phs0,rw/c1 receive overflow 1 pt phs0,rw/c1 packet transmitted 0 pr phs0,rw/c1 packet received 6.56 interrupt mask register (ffh) bit name default description 7 txrx_en phs0,rw enable the sram read/write pointer used as transmit /receive address. 6 reserved p0,ro reserved 5 lnkchgi phs0,rw enable link status change of port 0 or 1interrupt 4 cnt_err phs0,rw/c1 enable memory management error interrupt 3 rooi phs0,rw enable receive overflow counter overflow interrupt 2 roi phs0,rw enable receive overflow interrupt 1 pti phs0,rw enable packet transmitted interrupt 0 pri phs0,rw enable packet received interrupt DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 34 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 7. eeprom format name word description mac address 0~2 6 byte ethernet address auto load control 3 bit 1:0=01: update vendor id and product id bit 3:2=01: accept setting of word6 [4:0] bit 5:4= reserved bit 7:6= reserved, set to 00 in application bit 9:8=reserved bit 11:10= reserved, set to 00 in application bit 13:12= reserved bit 15:14=01: accept setting of word7 [15:12] vendor id 4 2-byte vendor id (default: 0a46h) pin control 6 when word 3 bit [3:2] =01, these bits can control the cs#, ior#, iow# and irq pins polarity. bit0: cs# pin is active high when set (default active low) bit1: ior# pin is active high when set (default: active low) bit2: iow# pin is active high when set (default: active low) bit3: irq pin is active low when set (default: active high) bit4: irq pin is open-collected (default: force output) bit 15:5: reserved phy control 7 bit11:0: reserved bit 13:12 reserved, set 00 in application bit14: port 1 auto-mdix control 1: on, 0: off(default on) bit15: port 0 auto-mdix control 1: on, 0: off(default on) reserved 8~15 reserved control 16 bit 1:0=01: accept setting of word 17,18 bit 3:2=01: accept setting of word 19~26 bit 5:4=01: accept setting of word 27~30 bit 7:6=01: accept setting of word 31 bit 9:8=01: accept setting of word 32~39 bit 11:10=01: accept setting of word 40~47 bit 15:12 = reserved, set 0000 in application switch control 1 17 when word 16 bit 1:0 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. 52h bit 7~0 this word bit 15~8 will be loaded to reg. 53h bit 7~0 switch control 2 18 when word 16 bit 1:0 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. 58h bit 7~0 this word bit 15~8 will be loaded to reg. 59h bit 7~0 port 0 control 1 19 when word 16 bit 3:2 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 0 reg. 61h bit 7~0 this word bit 15~8 will be loaded to port 0 reg. 66h bit 7~0 port 0 control 2 20 when word 16 bit 3:2 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 0 reg. 67h bit 7~0 this word bit 15~8 will be loaded to port 0 reg. 6dh bit 7~0 port 1 control 1 21 when word 16 bit 3:2 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 1 reg. 61h bit 7~0 this word bit 15~8 will be loaded to port 1 reg. 66h bit 7~0 port 1 control 2 22 when word 16 bit 3:2 is ?01?, after power on reset: DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 35 DM9302-15-ds-p01 july 30, 2009 this word bit 7~0 will be loaded to port 1 reg. 67h bit 7~0 this word bit 15~8 will be loaded to port 1 reg. 6dh bit 7~0 reserved 23~24 reserved up port control 1 25 when word 16 bit 3:2 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 3 reg. 61h bit 7~0 this word bit 15~8 will be loaded to port 3 reg. 66h bit 7~0 up port control 2 26 when word 16 bit 3:2 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 3 reg. 67h bit 7~0 this word bit 15~8 will be loaded to port 3 reg. 6dh bit 7~0 port 0 vlan tag 27 when word 16 bit 5:4 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 0 reg. 6eh bit 7~0 this word bit 15~8 will be loaded to port 0 reg. 6fh bit 7~0 port 1 vlan tag 28 when word 16 bit 5:4 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 1 reg. 6eh bit 7~0 this word bit 15~8 will be loaded to port 1 reg. 6fh bit 7~0 reserved 29 reserved up port vlan tag 30 when word 16 bit 5:4 is ?01?, after power on reset: this word bit 7~0 will be loaded to port 3 reg. 6eh bit 7~0 this word bit 15~8 will be loaded to port 3 reg. 6fh bit 7~0 vlan priority map 31 when word 16 bit 7:6 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. d0h bit 7~0 this word bit 15~8 will be loaded to reg. d1h bit 7~0 port vlan group 0,1 32 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. b0h bit 7~0 this word bit 15~8 will be loaded to reg. b1h bit 7~0 port vlan group 2,3 33 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. b2h bit 7~0 this word bit 15~8 will be loaded to reg. b3h bit 7~0 port vlan group 4,5 34 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. b4h bit 7~0 this word bit 15~8 will be loaded to reg. b5h bit 7~0 port vlan group 6,7 35 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. b6h bit 7~0 this word bit 15~8 will be loaded to reg. b7h bit 7~0 port vlan group 8,9 36 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. b8h bit 7~0 this word bit 15~8 will be loaded to reg. b9h bit 7~0 port vlan group 10,11 37 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. bah bit 7~0 this word bit 15~8 will be loaded to reg. bbh bit 7~0 port vlan group 12,13 38 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. bch bit 7~0 this word bit 15~8 will be loaded to reg. bdh bit 7~0 port vlan group 14,15 39 when word 16 bit 9:8 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. beh bit 7~0 this word bit 15~8 will be loaded to reg. bfh bit 7~0 tos priority map 0 40 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. c0h bit 7~0 this word bit 15~8 will be loaded to reg. c1h bit 7~0 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 36 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 tos priority map 1 41 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. c2h bit 7~0 this word bit 15~8 will be loaded to reg. c3h bit 7~0 tos priority map 2 42 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. c4h bit 7~0 this word bit 15~8 will be loaded to reg. c5h bit 7~0 tos priority map 3 43 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. c6h bit 7~0 this word bit 15~8 will be loaded to reg. c7h bit 7~0 tos priority map 4 44 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. c8h bit 7~0 this word bit 15~8 will be loaded to reg. c9h bit 7~0 tos priority map 5 45 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. cah bit 7~0 this word bit 15~8 will be loaded to reg. cbh bit 7~0 tos priority map 6 46 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. cch bit 7~0 this word bit 15~8 will be loaded to reg. cdh bit 7~0 tos priority map 7 47 when word 16 bit 11:10 is ?01?, after power on reset: this word bit 7~0 will be loaded to reg. ceh bit 7~0 this word bit 15~8 will be loaded to reg. cfh bit 7~0 reserved 53 set to 0 in application DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 37 DM9302-15-ds-p01 july 30, 2009 8. phy registers mii register description ad d name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset loop back speed select auto-n enable power down isolate restart auto-n full duplex coll. test reserved 00h contr ol 0 0 1 1 0 0 0 1 0 000_0000 t4 cap. tx fdx cap. tx hdx cap. 10 fdx cap. 10 hdx cap. reserved pream. supr. auto-n compl. remote fault auto-n cap. link status jabber detect extd cap. 01h statu s 0 1 1 1 1 0000 1 0 0 1 0 0 1 02h phyid1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 oui_lsb vndr_mdl mdl_rev 03h phyid2 101110 001011 0000 04h auto-ne g. advertis e next page flp rcv ack remote fault reserved fc adv t4 adv tx fdx adv tx hdx adv 10 fdx adv 10 hdx adv advertised protocol selector field 05h link part. ability lp next page lp ack lp rf reserved lp fc lp t4 lp tx fdx lp tx hdx lp 10 fdx lp 10 hdx link partner protocol selector field 06h auto-ne g. expansi on reserved pardet fault lp next pg able next pg able new pg rcv lp auton cap. 10h specifi ed config. bp 4b5b bp scr bp align bp_ad pok reserv edr tx reserv ed rmii mode force 100lnk rsvd . col led rpdct r-en reset st. mch pream. supr. sleep mode remote loopout 11h specifi ed conf/sta t 100 fdx 100 hdx 10 fdx 10 hdx reserv ed revers ed revers ed phy addr [4:0] auto-n. monitor bit [3:0] 12h 10t conf/sta t rsvd lp enable hbe enable sque enable jab enable serial reserved polarity reverse 13h pwdo r reserved pd10d rv pd100l pdchip pdcrm pdaeq pddrv pdecli pdeclo pd10 14h specifie d config tstse 1 tstse 2 force _txsd force _fef prea mblex tx10m _pwr nway _pwr reserv ed mdix_ cntl autone g_dlpbk mdix_fix value mdix_d own monsel 1 monsel 0 reserv ed pd_val ue 16h rcver receiver error counter 17h dis_con nect reversed disconnect_counter 1dh pscr reversed prea mble x amplit ude tx_p wr reversed key to default in the register description that follows, the default column takes the form: DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 38 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 8.1 basic mode control register (bmcr) ? 00h bit bit name default description 15 reset 0, rw/sc reset 1=software reset 0=normal operation this bit sets the status and controls the phy registers to their default states. this bit, which is self-clearing, will keep returning a value of one until the reset process is completed 14 loopback 0, rw loopback loop-back control register 1 = loop-back enabled 0 = normal operation when in 100mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the mii receive outputs 13 speed selection 1, rw speed select 1 = 100mbps 0 = 10mbps link speed may be selected either by this bit or by auto-negotiation. when auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 12 auto-negotiation enable 1, rw auto-negotiation enable 1 = auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status 11 power down 0, rw power down while in the power-down state, the phy should respond to management transactions. during the transition to power-down state and while in the power-down state, the phy should not generate spurious signals on the mii 1=power down 0=normal operation 10 isolate 0,rw isolate force to 0 in application. 9 restart auto-negotiation 0,rw/sc restart auto-negotiation 1 = restart auto-negotiation. re-initiates the auto-negotiation process. when auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9302. the operation of the auto-negotiation process will not be affected by the management entity that clears this bit 0 = normal operation 8 duplex mode 1,rw duplex mode 1 = full duplex operation. duplex selection is allowed when auto-negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bi t reflects the duplex capability selected by auto-negotiation 0 = normal operation DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 39 DM9302-15-ds-p01 july 30, 2009 7 collision test 0,rw collision test 1 = collision test enabled. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en in internal mii interface. 0 = normal operation 6-0 reserved 0,ro reserved read as 0, ignore on write 8.2 basic mode status register (bmsr) ? 01h bit bit name default description 15 100base-t4 0,ro/p 100base-t4 capable 1 = DM9302 is able to perform in 100base-t4 mode 0 = DM9302 is not able to perform in 100base-t4 mode 14 100base-tx full-duplex 1,ro/p 100base-tx full duplex capable 1 = DM9302 is able to perform 100base-tx in full duplex mode 0 = DM9302 is not able to perform 100base-tx in full duplex mode 13 100base-tx half-duplex 1,ro/p 100base-tx half duplex capable 1 = DM9302 is able to perform 100base-tx in half duplex mode 0 = DM9302 is not able to perform 100base-tx in half duplex mode 12 10base-t full-duplex 1,ro/p 10base-t full duplex capable 1 = DM9302 is able to perform 10base-t in full duplex mode 0 = DM9302 is not able to perform 10base-tx in full duplex mode 11 10base-t half-duplex 1,ro/p 10base-t half duplex capable 1 = DM9302 is able to perform 10base-t in half duplex mode 0 = DM9302 is not able to perform 10base-t in half duplex mode 10-7 reserved 0,ro reserved read as 0, ignore on write 6 mf preamble suppression 1,ro mii frame preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed 5 auto-negotiation complete 0,ro auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 4 remote fault 0, ro remote fault 1 = remote fault condition detected (cleared on read or by a chip reset). fault criteria and detection method is DM9302 implementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0 = no remote fault condition detected 3 auto-negotiation ability 1,ro/p auto configuration ability 1 = DM9302 is able to perform auto-negotiation 0 = DM9302 is not able to perform auto-negotiation 2 link status 0,ro link status 1 = valid link is established (for either 10mbps or 100mbps operation) 0 = link is not established the link status bit is implemented with a latching function, so that DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 40 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 1 jabber detect 0, ro jabber detect 1 = jabber condition detected 0 = no jabber this bit is implemented with a latching function. jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9302 reset. this bit works only in 10mbps mode 0 extended capability 1,ro/p extended capability 1 = extended register capable 0 = basic register capable only 8.3 phy id identifier register #1 (phyid1) ? 02h the phy identifier registers #1 and #2 work together in a single identifier of the DM9302. the identifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e. bit bit name default description 15-0 oui_msb <0181h> oui most significant bits this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the most significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2) 8.4 phy id identifier register #2 (phyid2) ? 03h bit bit name default description 15-10 oui_lsb <101110>, ro/p oui least significant bits bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 9-4 vndr_mdl <001011>, ro/p vendor model number five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3-0 mdl_rev <0000>, ro/p model revision number five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4) 8.5 auto-negotiation advertisement register (anar) ? 04h this register contains the advertised abilities of this DM9302 device as they will be transmitted to its link partner during auto-negotiation. bit bit name default description 15 np 0,ro/p next page indication 1 = next page available 0 = no next page available the DM9302 has no next page, so this bit is permanently set to 0 14 ack 0,ro acknowledge 1 = link partner ability data reception acknowledged DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 41 DM9302-15-ds-p01 july 30, 2009 0 = not acknowledged the DM9302's auto-negotiation state machine will automatically control this bit in the outgoing flp bursts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 13 rf 0, rw remote fault 1 = local device senses a fault condition 0 = no fault detected 12-11 reserved x, rw reserved write as 0, ignore on read 10 fcs 1, rw flow control support 1 = controller chip supports flow control ability 0 = controller chip doesn?t support flow control ability 9 t4 0, ro/p 100base-t4 support 1 = 100base-t4 is supported by the local device 0 = 100base-t4 is not supported the DM9302 does not support 100base-t4 so this bit is permanently set to 0 8 tx_fdx 1, rw 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the local device 0 = 100base-tx full duplex is not supported 7 tx_hdx 1, rw 100base-tx support 1 = 100base-tx half duplex is supported by the local device 0 = 100base-tx half duplex is not supported 6 10_fdx 1, rw 10base-t full duplex support 1 = 10base-t full duplex is supported by the local device 0 = 10base-t full duplex is not supported 5 10_hdx 1, rw 10base-t support 1 = 10base-t half duplex is supported by the local device 0 = 10base-t half duplex is not supported 4-0 selector <00001>, rw protocol selection bits these bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports ieee 802.3 csma/cd 8.6 auto-negotiation link partner ability register (anlpar) ? 05h this register contains the advertised abilities of th e link partner when received during auto-negotiation. bit bit name default description 15 np 0, ro next page indication 1 = link partner, next page available 0 = link partner, no next page available 14 ack 0, ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged the DM9302's auto-negotiation state machine will automatically control this bit from the incoming flp bursts. software should not attempt to write to this bit 13 rf 0, ro remote fault DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 42 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 12-11 reserved 0, ro reserved read as 0, ignore on write 10 fcs 0, ro flow control support 1 = controller chip supports flow control ability by link partner 0 = controller chip doesn?t support flow control ability by link partner 9 t4 0, ro 100base-t4 support 1 = 100base-t4 is supported by the link partner 0 = 100base-t4 is not supported by the link partner 8 tx_fdx 0, ro 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the link partner 0 = 100base-tx full duplex is not supported by the link partner 7 tx_hdx 0, ro 100base-tx support 1 = 100base-tx half duplex is supported by the link partner 0 = 100base-tx half duplex is no t supported by the link partner 6 10_fdx 0, ro 10base-t full duplex support 1 = 10base-t full duplex is supported by the link partner 0 = 10base-t full duplex is not supported by the link partner 5 10_hdx 0, ro 10base-t support 1 = 10base-t half duplex is supported by the link partner 0 = 10base-t half duplex is not supported by the link partner 4-0 selector <00000>, ro protocol selection bits link partner?s binary encoded protocol selector 8.7 auto-negotiation expansion register (aner) - 06h bit bit name default description 15-5 reserved 0, ro reserved read as 0, ignore on write 4 pdf 0, ro/lh local device parallel detection fault pdf = 1: a fault detected via parallel detection function. pdf = 0: no fault detected via parallel detection function 3 lp_np_able 0, ro link partner next page able lp_np_able = 1: link partner, next page available lp_np_able = 0: link partner, no next page 2 np_able 0,ro/p local device next page able np_able = 1: DM9302, next page available np_able = 0: DM9302, no next page DM9302 does not support this function, so this bit is always 0 1 page_rx 0, ro new page received a new link code word page received. this bit will be automatically cleared when the register (register 6) is read by management 0 lp_an_able 0, ro link partner auto-negotiation able a ?1? in this bit indicates that the link partner supports auto-negotiation DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 43 DM9302-15-ds-p01 july 30, 2009 8.8 davicom specified configuration register (dscr) ? 10h bit bit name default description 15 bp_4b5b 0,rw bypass 4b5b encoding and 5b4b decoding 1 = 4b5b encoder and 5b4b decoder function bypassed 0 = normal 4b5b and 5b4b operation 14 bp_scr 0, rw bypass scrambler/descrambler function 1 = scrambler and descrambler function bypassed 0 = normal scrambler and descrambler operation 13 bp_align 0, rw bypass symbol alignment function 1 = receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. transmit functions (symbol encoder and scrambler) bypassed 0 = normal operation 12 bp_adpok 0, rw bypass adpok force signal detector (sd) active. this register is for debug only, not release to customer 1: forced sd is ok, 0: normal operation 11 reserved rw reserved force to 0 in application 10 tx 1, rw 100base-tx mode control 1 = 100base-tx operation 0 = 100base-fx operation 9 reserved 0, ro reserved 8 reserved 0, rw reserved 7 f_link_100 0, rw force good link in 100mbps 1 = force 100mbps good link status 0 = normal 100mbps operation this bit is useful for diagnostic purposes 6 reserved 0, rw reserved force to 0 in application. 5 col_led 0, rw col led control (valid in phy test mode) 4 rpdctr-en 1, rw reduced power down control enable this bit is used to enable automatic reduced power down 1 = enable automatic reduced power down 0 = disable automatic reduced power down 3 smrst 0, rw reset state machine when writes 1 to this bit, all state machines of phy will be reset. this bit is self-clear after reset is completed 2 mfpsc 1, rw mf preamble suppression control mii frame preamble suppression control bit 1 = mf preamble suppression bit on 0 = mf preamble suppression bit off 1 sleep 0, rw sleep mode writing a 1 to this bit will cause phy entering the sleep mode and power down all circuit except osc illator and clock generator circuit. when waking up from sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 44 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 0 rlout 0, rw remote loop out control when this bit is set to 1, the re ceived data will loop out to the transmit channel. this is useful for bit error rate testing 8.9 davicom specified configuration and status register (dscsr) ? 11h bit bit name default description 15 100fdx 1, ro 100m full duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 14 100hdx 1, ro 100m half duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 13 10fdx 1, ro 10m full duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 12 10hdx 1, ro 10m half duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 11 reserved 0, ro reserved read as 0, ignore on write 10 reserved 0,rw reserved 9 reserved 0,rw reserved 8-4 phyadr[4:0] 1, rw phy address bit 4:0 the first phy address bit transmitted or received is the msb of the address (bit 4). a station management entity connected to multiple phy entities must know the appropriate address of each phy auto-negotiation monitor bits these bits are for debug only. the auto-n egotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 in idle state 0 0 0 1 ability match 0 0 1 0 acknowledge match 0 0 1 1 acknowledge match fail 0 1 0 0 consistency match 0 1 0 1 consistency match fail 0 1 1 0 parallel detects signal link ready 0 1 1 1 parallel detects signal link ready fail 3-0 anmb[3:0] 0, ro 1 0 0 0 auto-negotiation completed successfully DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 45 DM9302-15-ds-p01 july 30, 2009 8.10 10base-t configuration/status (10btcsr) ? 12h bit bit name default description 15 reserved 0, ro reserved read as 0, ignore on write 14 lp_en 1, rw link pulse enable 1 = transmission of link pulses enabled 0 = link pulses disabled, good link condition forced this bit is valid only in 10mbps operation 13 hbe 1,rw heartbeat enable 1 = heartbeat function enabled 0 = heartbeat function disabled when the DM9302 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) 12 squelch 1, rw squelch enable 1 = normal squelch 0 = low squelch 11 jaben 1, rw jabber enable enables or disables the jabber function when the DM9302 is in 10base-t full duplex or 10base-t transceiver loopback mode 1 = jabber function enabled 0 = jabber function disabled 10 serial 0, rw 10m serial mode (valid in phy test mode) force to 0, in application. 9-1 reserved 0, ro reserved read as 0, ignore on write 0 polr 0, ro polarity reversed when this bit is set to 1, it indicates that the 10mbps cable polarity is reversed. this bit is automatically set and cleared by 10base-t module 8.11 power down control register (pwdor) ? 13h bit bit name default description 15-9 reserved 0, ro reserved read as 0, ignore on write 8 pd10drv 0, rw vendor power down control test 7 pd100dl 0, rw vendor power down control test 6 pdchip 0, rw vendor power down control test 5 pdcrm 0, rw vendor power down control test 4 pdaeq 0, rw vendor power down control test 3 pddrv 0, rw vendor power down control test 2 pdedi 0, rw vendor power down control test 1 pdedo 0, rw vendor power down control test 0 pd10 0, rw vendor power down control test * when selected, the power down value is control by register 20.0 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 46 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 8.12 (specified config) register ? 14h bit bit name default description 15 tstse1 0,rw vendor test select 1 control 14 tstse2 0,rw vendor test select 2 control 13 force_txsd 0,rw force signal detect 1: force sd signal ok in 100m 0: normal sd signal. 12 force_fef 0,rw vendor test select control 11 preamblex 0,rw preamble saving control 0: when bit 10 is set, the 10base-t transmit preamble count is reduced. when bit 11 of register 1dh is set, 12-bit preamble is reduced; otherwise 22-bit preamble is reduced. 1: transmit preamble bit count is normal in 10base-t mode 10 tx10m_pwr 1,rw 10base-t mode transmit power saving control 1: enable transmit power saving in 10base-t mode 0: disable transmit power saving in 10base-t mode 9 nway_pwr 0,rw auto-negotiation power saving control 1: disable power saving during auto-negotiation period 0: enable power saving during auto-negotiation period 8 reserved 0, ro reserved read as 0, ignore on write 7 mdix_cntl mdi/mdix,ro the polarity of mdi/mdix value 1: mdix mode 0: mdi mode 6 autoneg_dpbk 0,rw auto-negotiation loopback 1: test internal digital auto-negotiation loopback 0: normal. 5 mdix_fix value 0, rw mdix_cntl force value: when mdix_down = 1, mdix_cntl value depend on the register value. 4 mdix_down 0,rw mdix down manual force mdi/mdix. 0: enable hp auto-mdix 1: disable hp auto-mdix , mdix_cntl value depend on reg.14h.bit5 3 monsel1 0,rw vendor monitor select 1 2 monsel0 0,rw vendor monitor select 0 1 reserved 0,rw reserved force to 0, in application. 0 pd_value 0,rw power down control value decision the value of each field reg.13h. 1: power down 0: normal DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 47 DM9302-15-ds-p01 july 30, 2009 8.13 davicom specified receive error counter register (recr) ? 16h bit bit name default description 15-0 rcv_ err_ cnt 0, ro receive error counter receive error counter that increments upon detection of rxer. clean by reading this register. 8.14 davicom specified disconnect counter register (discr) ? 17h bit bit name default description 15-8 reserved 0, ro reserved 7-0 disconnect counter 0, ro disconnect counter that increment upon detection of disconnection. clean by reading this register. 8.15 power saving control register (pscr) ? 1dh bit bit name default description 15-12 reserved 0,ro reserved 11 preamblex 0,rw preamble saving control when both bit 10 and 11 of register 14h are set, the 10base-t transmit preamble count is reduced. 1: 12-bit preamble is reduced. 0: 22-bit preamble is reduced. 10 amplitude 0,rw transmit amplitude control disabled 1: when cable is unconnected with link partner, the tx amplitude is reduced for power saving. 0: disable transmit amplitude reduce function 9 tx_pwr 0.rw transmit power saving control disabled 1: when cable is unconnected with link partner, the driving current of transmit is reduced for power saving. 0: disable transmit driving power saving function 8-0 reserved 0,ro reserved DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 48 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 9. functional description 9.1 processor bus and memory management function: 9.1.1 processor interface in the general processor mode, the chip selection is just coming from pin cs#. there are only two addressing ports through the access of the host interface. one port is the index port and the other is the data port. the index port is decoded by the cmd pin=0 and the data by the cmd pin=1. the contents of the index port are the register address of the data port. before the access of any register, the address of the register must be saved in the index port before. 9.1.2 direct memory access control the DM9302 provides dma capability to simplify the access of the internal memory. after the setting of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. the memory?s address will be increased wi th the size equal to the current operation mode (i.e. the byte or word mode) and the data of the next location will be loaded to internal data buffer automatically. it is noted that the data of the first access (the dummy read/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. there are two configured types of internal memory which are controlled by bit 7 of imr. when the bit 7 of imr is set, the internal memory is used for transmit and receive buffers. the transmit buffer occupies 8k bytes. and the receive buffer occupies 7.75k bytes. both the transmit and receive buffer address need not to be programmed instead that they are managed by the DM9302 automatically. in transmit function, after power on reset or each time after the transmit command is issued (bit 0 of tcr is set), the next starting transmit buffer address is loaded. in receive function, the 7.75k-byte receive buffer can be treated as a continued logic memory space. the memory address will wrap to address 0 if the end of address is reached. when the bit 7 of imr is cleared, there is a 64k- byte memory space in the DM9302 can be accessed. this configured type of in ternal memory is used for testing only. the memory write address (register fah/fbh) and the memory read address (register f4h/f5h) represent the physical memory address of the DM9302 internal memory. it is noted that after the memory had been written by memory write command, the switch reset command (bit 6 of register 52h) should be set before normal switch function operation, since the controlled data in internal memory may be corrupted. 9.1.3 packet transmission there are two packets, sequentially named as index i and index ii, can be stored in the tx sram at the same time. the index register 02h controls the insertion of crc. the start address of transmission is 00h and the current packet is index i after software or hardware reset. firstly write data to the tx sram using the dma port and then write the byte count to byte count register at index register 0fch and 0fdh. set the bit 1 of control register. the DM9302 starts to transmit the index i packet. before the transmission of the index i packet ends, the data of the next (index ii) packet can be moved to tx sram. after the index i packet ends the transmission, write the byte count data of the index ii to byte_count register and then set the bit 1 of control register to transmit the index ii packet. the following packets, named index i, ii, i, ii? use the same way to be transmitted. 9.1.4 packet reception the rx sram is a ring data structure. each packet has a 4-byte header followed with the data of the reception packet which crc field is included. the format of the 4-byte header is 01h, status, byte_count low, and byte_count high. it is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (byte or word mode). DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 49 DM9302-15-ds-p01 july 30, 2009 9.2 switch function: 9.2.1 address learning the DM9302 has a self-learning mechanism for learning the mac addresses of incoming packets in real time. DM9302 stores mac addresses, port number and time stamp information in the hash-based address table. it can learn up to 1k unicast address entry. the switch engine updates address table with new entry if incoming packet?s source address (sa) does not exist and incoming packet is valid (non-error and legal length). besides, DM9302 has an option to disable address learning for individual port. this feature can be set by bit 0 of register 65h 9.2.2 address aging the time stamp information of address table is used in the aging process. the switch engine updates time stamp whenever the corresponding sa receives. the switch engine would delete the entry if its time stamp is not updated for a period of time. the period can be programmed or disabled through bit 0 & 1 of register 52h. 9.2.3 packet forwarding the DM9302 forwards the incoming packet according to following decision: (1). if da is multicast/broadcast, the packet is forwarded to all ports, except to the port on which the packet was received. (2). switch engine would look up address table based on da when incoming packets is unicast. if the da was not found in address table, the packet is treated as a multicast packet and forward to other ports. if the da was found and its destination port number is different to source port number, the packet is forward to destination port. (3). switch engine also look up vlan, port monitor setting and other forwarding constraints for the forwarding decision, more detail will discuss in later sections. the DM9302 will filter incoming packets under following conditions: (1). error packets, including crc errors, alignment errors, illegal size errors. (2). pause packets. (3). if incoming pack et is unicast and its destination port number is equal to source port number. 9.2.4 inter-packet gap (ipg) ipg is the idle time between any two valid packets at the same port. the typical number is 96 bits time. in other word, the value is 9.6u sec for 10mbps and 960n sec for 100mbps. 9.2.5 back-off algorithm the DM9302 implements the binary exponential back-off algorithm in half-d uplex mode compliant to ieee standard 802.3. 9.2.6 late collision late collision is a type of collision. if a collision error occurs after the first 512 bit times of data are transmitted, the packet is dropped. 9.2.7 half duplex flow control the DM9302 supports ieee standard 802.3x flow control frames on both transmit and receive sides. on the receive side, the DM9302 will defer transmitting next normal frames, if it receives a pause frame from link partner. on the transmit side, the DM9302 issues pause frame with maximum pause time when internal resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. once resources are available, the DM9302 sends out a pause frame with zero pause time allows traffic to resume immediately. 9.2.8 full duplex flow control the DM9302 supports half-duplex backpressure. the inducement is the same as full duplex mode. when flow control is required, the DM9302 sends jam pattern, thus forcing a collision. the flow control ability can be set in bit 4 of register 61h. 9.2.9 partition mode the DM9302 provides a partition mode for each port, see bit 6 of register 61h. the port enters partition mode when more than 64 consecutive collisions are occurred. in partition mode the port continuous to transmit but it will not receive. the port returned to normal operation mode when a good DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 50 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 packet is seen on the wire. the detail description of partition mode represent following: (1). entering partition state a port will enter the partition state when either of the following conditions occurs: z the port detects a collision on every one of 64 consecutive re-transmit attempts to the same packet. z the port detects a single collision which occurs for more than 512 bit times. z transmit defer timer time out, which indicates the transmitting packet is deferred to long. (2). while in partition state: the port will continue to transmit its pending packet, regardless of the collision detection, and will not allow the usual back-off algorithm. additional packets pending for transmission will be transmitted, while ignoring the internal collision indication. this frees up the ports transmit buffers which would otherwise be filled up at the expense of other ports buffers. the assumption is that the partition is signifying a system failure situation (bad connection/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to a buffer full condition. (3). exiting from partition state the port exits from partition state, following the end of a successful packet transmission. a successful packet transmission is defined as no collisions were detected on the first 512 bits of the transmission. 9.2.10 broadcast storm filtering the DM9302 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from lower bandwidth availability. there are two type of broadcast storm control, one is throttling broadcast packet only, the other includes multicast. this feature can be set through bit 1 of register 61h. the broadcast storm threshold can be programmed by eeprom or register 67h, the default setting is no broadcast storm protecting. 9.2.11 bandwidth control the DM9302 supports two type of bandwidth control for each port. one is the ingress and egress bandwidth rate can be control separately, the other is combined together, this function can be set through bit 3 of register 61h. the bandwidth control is disabled by default. for separated bandwidth control mode, the threshold rate is defined in register 66h. for combined mode, it is defined in register 67h. the behavior of bandwidth control as below: (1).for the ingress control, if flow control function is enabled, pause or jam pa cket will be transmitted. the ingress packets will be dropped if flow control is disabled. (2).for the egress control, the egress port will not transmit any packets. on the other hand, the ingress bandwidth of source port w ill be throttled that prevent packets from forwarding. (3).in combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will be throttled. 9.2.12 port monitoring support the DM9302 supports ?port monitoring? function on per port base, detail as below: (1). sniffer port and monitor port there is only one port can be selected as ?sniffer port? by register 52h, multiple ports can be set as ?receive monitor port? or ?transmit monitor port? in per-port register 65h. (2).receive monitor all packets received on the ?receive monitor port? are send a copy to ?sniffer port?. for example, port 0 is set as ?receive monitor port? and port 3 (processor port) is selected as ?sniffer port?. if a packet is received form port 0 and destined to port 1 after forwarding decision, the DM9302 will forward it to port 1 and processor port in the end. (3).transmit monitor all packets transmitted on the ?transmit monitor port? are send a copy to ?sniffer port?. for example, port 1 is set as ?transmit monitor port? and processor port is selected as ?sniffer port?. if a packet is received from port 0 and predestined to port 1 after forwarding decision, the DM9302 will forward it to port 1 and processor port in the end. (4).exception the DM9302 has an optional setting that broadcast/multicast packets are not monitored (see bit 4 of register 65h). it?s useful to avoid unnecessary bandwidth. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 51 DM9302-15-ds-p01 july 30, 2009 9.2.13 vlan support 9.2.13.1 port-based vlan the DM9302 supports port-based vlan as default, up to 16 groups. each port has a default vid called pvid (port vid, see register 6fh). the DM9302 used lsb 4-bytes of pvid as index and mapped to register b0h~bfh, to define the vlan groups. 9.2.13.2 802.1q-based vlan regarding ieee 802.1q standard, tag-based vlan uses an extra tag to identify the vlan membership of a frame across vlan-aware switch/router. a tagged frame is four bytes longer than an untagged frame and contains two bytes of tpid (tag protocol identifier) and two bytes of tci (tag control information). dest. src. length/type data dest. src. tpid data tci length / type priority cfi vid standard frame tagged frame 0x8100 2 bytes 3 bits 1 bits 12 bits the DM9302 also supports 16 802.1q-based vlan groups, as specified in bit 1 of register 53h. it?s obvious that the tagged packets can be assigned to several different vlans which are determined according to the vid inside the vlan tag. therefore, the operation is similar to port-based vlan. the DM9302 used lsb 4-bytes vid of received packet with vlan tag and vlan group mapping register (b0h~bfh) to configure the vlan partition. if the destination port of received packet is not same vlan group with received port, it will be discarded. 9.2.13.3 tag/untag user can define each port as tag port or un-tag port by bit 7 of register 6dh in 802.1q-based vlan mode. the operation of tag and un-tag can explain as below conditions: (1). receive untagged packet and forward to un-tag port. received packet will forward to destination port without modification. (2). receive tagged packet and forward to un-tag port. the DM9302 will remove the tag from the packet and recalculate crc before sending it out. (3). receive untagged packet and forward to tag port. the DM9302 will insert the pvid tag when an untagged packet enters the port, and recalculate crc before delivering it. (4). receive tagged packet and forward to tag port. received packet will forward to destination port without modification. 9.2.14 priority support the DM9302 supports quality of service (qos) mechanism for multimedia communication such as voip and video conferencing. the DM9302 provides three priority classifications: port-based, 802.1p-based and diffserv-based priority. see next section for more detail. the DM9302 offers four level queues for transmit on per-port based. the DM9302 provides two packet scheduling algorithms: weighted round-robin queuing and DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 52 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 strict priority queuing. weighted round-robin queuing (wrr) based on their priority and queue weight. queues with larger weights get more service than smaller. this mechanism can get highly efficient bandwidth and smooth the traffic. strict priority queuing (spq) based on priority only. the packet on the highest priority queue is transmitted first. the next highest-priority queue is work until last queue empties, and so on. this feature can be set in bit 5 of register 6dh. 9.2.14.1 port-based priority port based priority is the simplest scheme and as default. each port has a 2-bit priority value as index for splitting ingress packets to the corresponding transmit queue. this value can be set in bit 0 and 1 of register 6dh. 9.2.14.2 802.1p-based priority 802.1p priority can be disabled by bit 2 of register 6dh, it is enabled by default. the DM9302 extracts 3-bit priority field from received packet with 802.1p vlan tag, and maps this field against vlan priority map registers (d0h~d1h) to determine which transmit queue is designated. the vlan priority map is programmable. 9.2.14.3 diffserv-based priority diffserv based priority uses the most significant 6-bit of the tos field in standard ipv4 header, and maps this field against tos priority map registers (c0h~cfh) to determine which transmit queue is designated. the tos priority map is programmable too. in addition, user can only refer to most significant 3-bit of the tos field optionally, see bit 7 of register 53h. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 53 DM9302-15-ds-p01 july 30, 2009 9.3 internal phy functions 9.3.1 100base-tx operation the transmitter section contains the following functional blocks: - 4b5b encoder - scrambler - parallel to serial converter - nrz to nrzi converter - nrzi to mlt-3 - mlt-3 driver 9.3.1.1 4b5b encoder the 4b5b encoder converts 4-bit (4b) nibble data generated by the mac reconciliation layer into a 5-bit (5b) code group for transmission, see reference table 1. this conversion is required for control and packet data to be combined in code groups. the 4b5b encoder substitutes the first 8 bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmit. the 4b5b encoder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code-groups. at the end of the transmit packet, upon the deassertion of the transmit enable signal from the mac reconciliation layer, the 4b5b encoder injects the t/r code-group pair (01101 00111) indicating the end of frame. after the t/r code-group pair, the 4b5b encoder continuously injects idles into the transmit data stream until transmit enable is asserted and the next transmit packet is detected. 9.3.1.2 scrambler the scrambler is required to control the radiated emissions (emi) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100base-tx operation. by scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. without the scrambler, energy levels on the cable could peak beyond fcc limitations at frequencies related to the repeated 5b sequences, like the continuous transmission of idle symbols. the scrambler outp ut is combined with the nrz 5b data from the code-group encoder via an xor logic function. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 9.3.1.3 parallel to serial converter the parallel to serial conv erter receives parallel 5b scrambled data from the scrambler, and serializes it (converts it from a parallel to a serial data stream). the serialized data stream is then presented to the nrz to nrzi encoder block 9.3.1.4 nrz to nrzi encoder after the transmit data stream has been scrambled and serialized, the data must be nrzi encoded for compatibility with the tp-p md standard, for 100base -tx transmission over category-5 unshielded twisted pair cable. 9.3.1.5 mlt-3 converter the mlt-3 conversion is accomplished by converting the data stream output, from the nrzi encoder into two binary data streams, with alternately phased logic one event. 9.3.1.6 mlt-3 driver the two binary data streams created at the mlt-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer?s primary winding, resulting in a minimal current mlt-3 signal. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 54 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 9.3.1.7 4b5b code group symbol meaning 4b code 3210 5b code 43210 0 data 0 0000 11110 1 data 1 0001 01001 2 data 2 0010 10100 3 data 3 0011 10101 4 data 4 0100 01010 5 data 5 0101 01011 6 data 6 0110 01110 7 data 7 0111 01111 8 data 8 1000 10010 9 data 9 1001 10011 a data a 1010 10110 b data b 1011 10111 c data c 1100 11010 d data d 1101 11011 e data e 1110 11100 f data f 1111 11101 i idle undefined 11111 j sfd (1) 0101 11000 k sfd (2) 0101 10001 t esd (1) undefined 01101 r esd (2) undefined 00111 h error undefined 00100 v invalid undefined 00000 v invalid undefined 00001 v invalid undefined 00010 v invalid undefined 00011 v invalid undefined 00101 v invalid undefined 00110 v invalid undefined 01000 v invalid undefined 01100 v invalid undefined 10000 v invalid undefined 11001 table 1 DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 55 DM9302-15-ds-p01 july 30, 2009 9.3.2 100base-tx receiver the 100base-tx receiver contains several function blocks that convert the scrambled 125mb/s serial data to synchronous 4-bit nibble data. the receive section contains the following functional blocks: - signal detect - digital adaptive equalization - mlt-3 to binary decoder - clock recovery module - nrzi to nrz decoder - serial to parallel - descrambler - code group alignment - 4b5b decoder 9.3.2.1 signal detect the signal detects function meets the specifications mandated by the ansi xt12 tp-pmd 100base-tx standards for both voltage thresholds and timing parameters. 9.3.2.2 adaptive equalization when transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a concern. in high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. this variation in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the received data. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation that includes shorter, less attenuating cable lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. 9.3.2.3 mlt-3 to nrzi decoder the DM9302 decodes the mlt-3 information from the digital adaptive equalizer into nrzi data. 9.3.2.4 clock recovery module the clock recovery module accepts nrzi data from the mlt-3 to nrzi decoder. the clock recovery module locks onto the data stream and extracts the 125 mhz reference clock. the extracted and synchronized clock and data are presented to the nrzi to nrz decoder. 9.3.2.5 nrzi to nrz the transmit data stream is required to be nrzi encoded for compatibility wi th the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. this conversion process must be reversed on the receive end. the nrzi to nrz decoder receives the nrzi data stream from the clock recovery module and converts it to a nrz data stream to be presented to the serial to parallel conversion block. 9.3.2.6 serial to parallel the serial to parallel converter receives a serial data stream from the nrzi to nrz converter. it converts the data stream to parallel da ta to be presented to the descrambler. 9.3.2.7 descrambler because of the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. the descrambler receives scrambled parallel data streams from the serial to parallel converter, and it descrambles the data streams, and presents the data streams to the code group alignment block. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 56 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 9.3.2.8 code group alignment the code group alignment block receives un-aligned 5b data from the descrambler and converts it into 5b code group data. code group alignment occurs after the j/k is detected and subsequent data is aligned on a fixed boundary. 9.3.2.9 4b5b decoder the 4b5b decoder functions as a look-up table that translates incoming 5b code groups into 4b (nibble) data. when receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (j/k symbols). the j/k symbol pair is stripped and two nibbles of preamble pattern are substituted. the last two code groups are the end-of-frame delimiter (t/r symbols). the t/r symbol pair is also stripped from the nibble, presented to the reconciliation layer. 9.3.3 10base-t operation the 10base-t transceiver is ieee 802.3u compliant. when the DM9302 is operating in 10base-t mode, the coding scheme is manchester. data processed for transmit is presented in nibble format, converted to a serial bit stream, then the manchester encoded. when receiving, the bit stream, encoded by the manchester, is decoded and converted into nibble format. 9.3.4 collision detection for half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. collision detection is disabled in full duplex operation. 9.3.5 carrier sense carrier sense (crs) is asserted in half-duplex operation during transmission or reception of data. during full-duplex mode, crs is asserted only during receive operations. 9.3.6 auto-negotiation the objective of auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. it is important to note that auto-negotiation does not test the characteristics of the linked segment. the auto-negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. this allows devices on both ends of a segment to establish a link at the best common mode of operation. if more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. auto-negotiation also provides a parallel detection function for devices that do not support the auto-negotiation feature. during parallel detection there is no exchange of information of configuration. instead, the receive signal is examined. if it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. this allows devices not to support auto-negotiation but support a common mode of operation to establish a link. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 57 DM9302-15-ds-p01 july 30, 2009 10. dc and ac electrical characteristics 10.1 absolute maximum ratings symbol parameter min. max. unit conditions vcc3 3.3v supply voltage -0.3 3.6 v - vcci 1.8v core power supply -0.3 1.95 v - avdd3 analog power supply 3.3v -0.3 3.6 v - avddi analog power supply 1.8v -0.3 1.95 v - v in dc input voltage (vin) -0.5 5.5 v - t stg storage temperature range -65 +150 c - t a ambient temperature 0 +70 c - l t lead temperature (tl, soldering, 10 sec.). - +260 c lead-free device 10.2 operating conditions symbol parameter min. typ. max. unit conditions vcc3 3.3v supply voltage 3.135 3.300 3.465 v - vcci 1.8v core power supply 1.71 1.80 1.89 v - avdd3 analog power supply 3.3v 3.135 3.300 3.465 v - avddi analog power supply 1.8v 1.71 1.80 1.89 v - - 90 - ma 1.8vd only - 120 - ma 1.8va only - 20 - ma 3.3vd only 100base-tx with 100base-fx data utilization rate is 100% - 50 - ma 3.3va only - 90 - ma 1.8vd only - 110 - ma 1.8va only - 40 - ma 3.3vd only ethernet link o.k. - 40 - ma 3.3va only - 90 - ma 1.8vd only - 120 - ma 1.8va only - 60 - ma 3.3vd only fiber link o.k. - 20 - ma 3.3va only - 80 - ma 1.8vd only - 80 - ma 1.8va only - 30 - ma 3.3vd only p d (power dissipation) auto-negotiation or cable off - 40 - ma 3.3va only DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 58 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 10.3 dc electrical characteristics symbol parameter min. typ. max. unit conditions inputs vil input low voltage - - 0.8 v vcond1 vih input high voltage 2.0 - - v vcond1 iil input low leakage current -1 - - ua vin = 0.0v, vcond1 iih input high leakage current - - 1 ua vin = 3.3v, vcond1 outputs vol output low voltage - - 0.4 v iol =4ma voh output high voltage 2.4 - - v ioh = -4ma receiver vicm rx+/rx- common mode input voltage - 1.8 - v 100 termination across transmitter vtd100 100tx+/- differential output voltage 1.9 2.0 2.1 v peak to peak vtd10 10tx+/- differential output voltage 4.0 5 5.6 v peak to peak itd100 100tx+/- differential output current 19 20 21 ma absolute value itd10 10tx+/- differential output current 40 50 56 ma absolute value note: vcond1 = vcc3 = 3.3v, vcci = 1.8v, avdd3 = 3.3v, avddi = 1.8v. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 59 DM9302-15-ds-p01 july 30, 2009 10.4 ac characteristics 10.4.1 power on reset timing pwrst# strap pins t2 t1 eecs t3 t4 t5 cs# symbol parameter min. typ. max. unit conditions t1 pwrst# low period 1 - - ms - t2 strap pin hold time with pwrst# 40 - - ns - t3 pwrst# high to eecs high - 5 - us - t4 pwrst# high to eecs burst end - -- 4 ms - t5 pwrst# high to cs# available -- 400 -- us - DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 60 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 10.4.2 processor i/o read timing ior# sd0~15 cs#,cmd t1 t2 t3 t4 t5 t6 symbol parameter min. typ. max. unit t1 cs#,cmd valid to ior# valid 5 ns t2 ior# invalid to cs#,cmd invalid 5 ns t3 ior# width 20 ns t4 ior# invalid to next ior#/iow# valid when read DM9302 register 2 clk *1 t4 ior# invalid to next ior#/iow# valid when read DM9302 memory with f0h register 4 clk *1 t3+t4 ior# invalid to next ior#/iow# valid when read DM9302 memory with f2h register 1 clk *1 t5 system data(sd) delay time 25 ns t6 ior# invalid to system data(sd) invalid 10 ns *1 : the unit: clk is under the internal system clock 50mhz.(20ns). DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 61 DM9302-15-ds-p01 july 30, 2009 10.4.3 processor i/o write timing iow# sd0~15 cs#,cmd t1 t2 t3 t4 t5 t6 symbol parameter min. typ. max. unit t1 cs#,cmd valid to iow# valid 5 ns t2 iow# invalid to cs#,cmd invalid 5 ns t3 iow# width 20 ns t4 iow# invalid to next iow#/ior# valid when write DM9302 index port 1 clk *1 t4 iow# invalid to next iow#/ior# valid when write DM9302 data port 2 clk *1 t3+t4 iow# invalid to next iow#/ior# valid when write DM9302 memory 1 clk *1 t5 system data(sd) setup time 5 ns t6 system data(sd) hold time 3 ns *1 : the unit: clk is under the internal system clock 50mhz.(20ns). DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 62 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 10.4.4 eeprom timing eecs eeck eedio t1 t2 t3 t4 t5 t6 t7 symbol parameter min. typ. max. unit t1 eecs setup time 480 ns t2 eecs hold time 2080 ns t3 eeck frequency 0.38 mhz t4 eedio setup time in output state 460 ns t5 eedio hold time in output state 2100 ns t6 eedio setup time in input state 8 ns t7 eedio hold time in input state 8 ns DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus preliminary datasheet 63 DM9302-15-ds-p01 july 30, 2009 11. package information 64 pins lqfp package outline information: dimension in mm dimension in inch symbol min nom max min nom max a - - 1.60 - - 0.063 a 1 0.05 - 0.15 0.002 - 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 b 1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 - 0.20 0.004 - 0.008 c 1 0.09 - 0.16 0.004 - 0.006 d 12.00 bsc 0.472 bsc d 1 10.00 bsc 0.394 bsc e 12.00 bsc 0.472 bsc e 1 10.00 bsc 0.394 bsc e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref 0.039 ref r 1 0.08 - - 0.003 - - r 2 0.08 - 0.20 0.003 - 0.008 s 0.20 - - 0.008 - - 0 o 3.5 o 7 o 0 o 3.5 o 7 o 1 0 o - - 0 o - - 2 12 o typ 12 o typ 3 12 o typ 12 o typ 1. dimension d 1 and e 1 do not include resin fin. 2. all dimensions are base on metric system. 3. general appearance spec should base on its final visual inspection spec. DM9302 10/100mbps ethernet fiber/twisted pair media converter with local bus 64 preliminary datasheet DM9302-15-ds-p01 july 30, 2009 12. ordering information part number pin count package DM9302ep 64 lqfp (pb-free) disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrate d in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no.6 li-hsin rd. vi, science-based park, hsin-chu city, taiwan, r.o.c. tel: + 886-3-5798797 fax: + 886-3-5646929 e-mail: sales@davicom.com.tw web: http://www.davicom.com.tw warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function . |
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